Title: Realization of basic gates & Boolean function using dataflow modelling.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity allgate is
Port ( a,b : in STD_LOGIC;
c ,d,e,f,g,h,i: out STD_LOGIC);
end allgate;
architecture dataflow of allgate is
begin
c<=a and b;
d<=a or b;
e<=not(a);
f<=a xor b;
g<=a xnor b;
h<=a nand b;
i<=a nor b;
end dataflow;
RTL Schematic:
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_allgate IS
END tb_allgate;
ARCHITECTURE behavior OF tb_allgate IS
COMPONENT allgate
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic;
d : OUT std_logic;
e : OUT std_logic;
f : OUT std_logic;
g : OUT std_logic;
h : OUT std_logic;
i : OUT std_logic
);
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
signal d : std_logic;
signal e : std_logic;
signal f : std_logic;
signal g : std_logic;
signal h : std_logic;
signal i : std_logic;
BEGIN
uut: allgate PORT MAP (
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
h => h,
i => i
);
stim_proc: process
begin
a <= '0';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for 100 ns;
wait;
end process;
END;
Title: Implementation of half adder & full adder using dataflow
modeling.
1)HALF ADDER:
DATAFLOW MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end halfadder;
architecture dataflow of halfadder is
begin
sum<=((NOT A)AND B)OR(A AND (NOT B));
carry<=A AND B;
end dataflow;
BEHAVIORAL MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
sum<=A XOR B;
carry<=A AND B;
end Behavioral;
STRUCTURAL MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end halfadder;
architecture structural of halfadder is
component andgate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component xorgate is
Port ( m : in STD_LOGIC;
n : in STD_LOGIC;
o : out STD_LOGIC);
end component;
begin
xr:xorgate port map(m=>A,n=>B,o=>sum);
ad:andgate port map(x=>B,y=>A,z=>carry );
end structural;
TEST BENCH CODE:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_halfadder IS
END TB_halfadder;
ARCHITECTURE behavior OF TB_halfadder IS
COMPONENT halfadder
PORT(
A : IN std_logic;
B : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;
BEGIN
uut: halfadder PORT MAP (
A => A,
B => B,
sum => sum,
carry => carry
);
process
begin
a<='0';
b<='0';
wait for 100 ns;
a<='0';
b<='1';
wait for 100 ns;
a<='1';
b<='0';
wait for 100 ns;
a<='1';
b<='1';
wait for 100 ns;
wait;
end process;
END;
2)FULL ADDER:
DATAFLOW MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder;
architecture dataflow of fulladder is
begin
sum<=((not A) and (NOT B)AND C)OR ((NOT A)and B AND(NOT C))OR(A AND (NOT B)AND(NOT C))OR(A
AND B AND C);
carry<=((NOT A)AND B AND C)OR(A AND (NOT B)AND C)OR(A AND B AND C)OR (A AND B AND(NOT C));
end dataflow;
BEHAVIORAL MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
cout : out STD_LOGIC;
sum : out STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
begin
sum<=A XOR B XOR C;
cout<=(B AND C)OR(A AND C)OR(A AND B);
end Behavioral;
STUCTURAL MODELING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder;
architecture structural of fulladder is
component halfadder is
Port ( I1 : in STD_LOGIC;
I2: in STD_LOGIC;
S : out STD_LOGIC;
D : out STD_LOGIC);
end component;
component orgate is
Port ( I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
X : out STD_LOGIC);
end component;
signal S1,C1,C2:STD_LOGIC;
begin
INST_HA1:halfadder port map(I1=>B,I2=>C,S=>S1,D=>C1);
INST_HA2:halfadder port map(I1=>A,I2=>S1,S=>sum,D=>C2);
INST_OR:orgate port map(I1=>C2,I2=>C1,X=>carry);
end structural;
Test Bench For FULL ADDER:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_FULLADDER IS
END TB_FULLADDER;
ARCHITECTURE behavior OF TB_FULLADDER IS
COMPONENT fulladder
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
cout : OUT std_logic;
sum : OUT std_logic
);
END COMPONENT
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
--Outputs
signal cout : std_logic;
signal sum : std_logic;
BEGIN
uut: fulladder PORT MAP (
A => A,
B => B,
C => C,
cout => cout,
sum => sum
);
-- Stimulus process
stim_proc: process
begin
A<='0';
B<='0';
C<='0';
wait for 100 ns;
A<='0';
B<='0';
C<='1';
wait for 100 ns;
A<='0';
B<='1';
C<='0';
wait for 100 ns;
A<='0';
B<='1';
C<='1';
wait for 100 ns;
A<='1';
B<='0';
C<='0';
wait for 100 ns;
A<='1';
B<='0';
C<='1';
wait for 100 ns;
A<='1';
B<='1';
C<='0';
wait for 100 ns;
A<='1';
B<='1';
C<='1';
wait for 100 ns;
wait;
end process;
END;
Title: Implementation of 3:8 decoder using WITH-SELECT and PROCESS-CASE statements.
a) 3:8 decoder using WITH-SELECT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder3to8 is
Port ( g1 : in STD_LOGIC;
g2 : in STD_LOGIC;
g3 : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder3to8;
architecture Behavioral of decoder3to8 is
signal l:std_logic_vector(7 downto 0);
begin
with a select l <= "01111111" when "000",
"10111111" when "001",
"11011111" when "010",
"11101111" when "011",
"11110111" when "100",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when others;
y<=l when(g1 and(not g2) and (not g3)) = '1' else
"11111111";
end Behavioral;
b) 3:8 decoder using PROCESS-CASE statements.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder3_8 is
Port ( g1 : in STD_LOGIC;
g2 : in STD_LOGIC;
g3 : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder3_8;
architecture Behavioral of decoder3_8 is
signal i : std_logic_vector(7 downto 0);
begin
process(i,a,g1,g2,g3)
begin
case a is
when "000" => i <= "10000000";
when "001" => i <= "01000000";
when "010" => i <= "00100000";
when "011" => i <= "00010000";
when "100" => i <= "00001000";
when "101" => i <= "00000100";
when "110" => i <= "00000010";
when "111" => i <= "00000001";
when others => i<= "00000000";
end case;
if(g1 and g2 and g3) = '1' then y <= i;
else y <= "00000000";
end if;
end process;
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_decoder3to8 IS
END tb_decoder3to8;
ARCHITECTURE behavior OF tb_decoder3to8 IS
COMPONENT decoder3to8
PORT(
g1 : IN std_logic;
g2 : IN std_logic;
g3 : IN std_logic;
a : IN std_logic_vector(2 downto 0);
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal g1 : std_logic := '0';
signal g2 : std_logic := '0';
signal g3 : std_logic := '0';
signal a : std_logic_vector(2 downto 0) := (others => '0');
signal y : std_logic_vector(7 downto 0);
BEGIN
uut: decoder3to8 PORT MAP (
g1 => g1,
g2 => g2,
g3 => g3,
a => a,
y => y
);
stim_proc: process
begin
-- hold reset state for 100 ns.
g1<='0';
g2<='0';
g3<='0';
a<="000";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="000";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="001";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="010";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="011";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="100";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="101";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="110";
wait for 100 ns;
g1<='1';
g2<='0';
g3<='0';
a<="111";
wait for 100 ns;
wait;
end process;
END;
Title: Implementation of 4:1 Multiplexer & 3-Bit Priority Encoder using when-
else statement.
a)4 : 1 Multiplexer using when-else statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4 is
Port ( a, b, c, d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end Mux4;
architecture Behavioral of Mux4 is
begin
y <= a when s="00" else
b when s="01" else
c when s="10" else
d;
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_mux4 IS
END tb_mux4;
ARCHITECTURE behavior OF tb_mux4 IS
COMPONENT mux4
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
s : IN std_logic_vector(1 downto 0);
z : OUT std_logic
);
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal z : std_logic;
BEGIN
uut: mux4 PORT MAP (
a => a,
b => b,
c => c,
d => d,
s => s,
z => z
);
stim_proc: process
begin
a <= '0';
b <= '1';
c <= '1';
d <= '1';
s <= "00";
wait for 100 ns;
a <= '0';
b <= '1';
c <= '1';
d <= '1';
s <= "01";
wait for 100 ns;
a <= '0';
b <= '1';
c <= '1';
d <= '1';
s <= "10";
wait for 100 ns;
a <= '0';
b <= '1';
c <= '1';
d <= '1';
s <= "11";
wait for 100 ns;
wait;
end process;
END;
b) 3-Bit Priority Encoder using when-else statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Encoder3 is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
o : out STD_LOGIC_VECTOR (2 downto 0));
end Encoder3;
architecture Behavioral of Encoder3 is
begin
o <= "000" when i(0)='1' else
"001" when i(1)='1' else
"010" when i(2)='1' else
"011" when i(3)='1' else
"100" when i(4)='1' else
"101" when i(5)='1' else
"110" when i(6)='1' else
"111" when i(7)='1' else
"000";
end Behavioral;
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Encoder3 IS
END tb_Encoder3;
ARCHITECTURE behavior OF tb_Encoder3 IS
COMPONENT Encoder3
PORT(
i : IN std_logic_vector(7 downto 0);
o : OUT std_logic_vector(2 downto 0));
END COMPONENT;
signal i : std_logic_vector(7 downto 0) := (others => '0');
signal o : std_logic_vector(2 downto 0);
BEGIN
uut: Encoder3 PORT MAP (
i => i,
o => o
);
stim_proc: process
begin
i<= "00000001";
wait for 100 ns;
i<= "00000010";
wait for 100 ns;
i<= "00000100";
wait for 100 ns;
i<= "00001000";
wait for 100 ns;
i<= "00010000";
wait for 100 ns;
i<= "00100000";
wait for 100 ns;
i<= "01000000";
wait for 100 ns;
i<= "10000000";
wait for 100 ns;
wait;
end process;
END;
Title: Implementation of 8-bit Shift Register with positive edge clock.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register is
Port ( C,SI : in STD_LOGIC;
SO : out STD_LOGIC);
end shift_register;
architecture Behavioral of shift_register is
SIGNAL TEMP: STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
begin
PROCESS(C)
BEGIN
IF(C'EVENT AND C='1')THEN
FOR I IN 0 TO 6 LOOP
TEMP(I+1)<=TEMP(I);
END LOOP;
TEMP(0)<= SI;
END IF;
END PROCESS;
SO<=TEMP(7);
end Behavioral;
3 bit priority encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder is
Port ( sel : in STD_LOGIC_VECTOR (7 downto 0);
code : out STD_LOGIC_VECTOR (2 downto 0));
end encoder;
architecture dataflow of encoder is
begin
code<="000"when sel(0)='1'else
"001"when sel(1)='1'else
"010"when sel(2)='1'else
"011"when sel(3)='1'else
"100"when sel(4)='1'else
"101"when sel(5)='1'else
"110"when sel(6)='1'else
"111"when sel(7)='1'else
"XXX";
end dataflow;
test bench code :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_encoder IS
END TB_encoder;
ARCHITECTURE dataflow OF TB_encoder IS
COMPONENT encoder
PORT(
sel : IN std_logic_vector(7 downto 0);
code : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal sel : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal code : std_logic_vector(2 downto 0);
BEGIN
uut: encoder PORT MAP (
sel => sel,
code => code
);
stim_proc: process
begin
sel<="00000001";
wait for 100 ns;
sel<="00000010";
wait for 100 ns;
sel<="00000100";
wait for 100 ns;
sel<="00001000";
wait for 100 ns;
sel<="00010000";
wait for 100 ns;
sel<="00100000";
wait for 100 ns;
sel<="01000000";
wait for 100 ns;
sel<="10000000";
wait for 100 ns;
wait;
end process;
END;
Title: Implementation of 4 bit Ripple Adder using structural type of modeling.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Fulladder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end Fulladder;
architecture Structural of Fulladder is
component Halfadder is
Port ( m : in STD_LOGIC;
n : in STD_LOGIC;
o : out STD_LOGIC;
p : out STD_LOGIC);
end component;
component orgate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
signal s1,c1,c2: std_logic;
begin
half1: Halfadder port map(m=>b,n=>ci,o=>s1,p=>c1);
half2: halfadder port map(m=>a,n=>s1,o=>s,p=>c2);
org: orgate port map(x=>c2,y=>c1,z=>co);
end Structural;
Halfadder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Halfadder is
Port ( m : in STD_LOGIC;
n : in STD_LOGIC;
o : out STD_LOGIC;
p : out STD_LOGIC);
end Halfadder;
architecture Behavioral of Halfadder is
begin
o <= m xor n;
p <= m and n;
end Behavioral;
OR Gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity orgate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end orgate;
architecture Behavioral of orgate is
begin
z <= x or y;
end Behavioral;
Full Adder Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_FulladderBehavioral IS
END tb_FulladderBehavioral;
ARCHITECTURE behavior OF tb_FulladderBehavioral IS
COMPONENT Fulladder
PORT(
a : IN std_logic;
b : IN std_logic;
ci : IN std_logic;
s : OUT std_logic;
co : OUT std_logic
);
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal ci : std_logic := '0';
signal s : std_logic;
signal co : std_logic;
BEGIN
uut: Fulladder PORT MAP (
a => a,
b => b,
ci => ci,
s => s,
co => co
);
stim_proc: process
begin
a <= '0';
b <= '0';
ci <= '0';
wait for 100 ns;
a <= '0';
b <= '0';
ci <= '1';
wait for 100 ns;
a <= '0';
b <= '1';
ci <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
ci <= '1';
wait for 100 ns;
a <= '1';
b <= '0';
ci <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
ci <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
ci <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
ci <= '1';
wait for 100 ns;
wait;
end process;
END;
Title: Implementation of 3-bit sequence detector using VHDL.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sequencedetector is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end sequencedetector;
architecture Behavioral of sequencedetector is
type seq_det_states is (start,one1,two1s,found_it);
signal seq_det_ps,seq_det_ns:seq_det_states;
begin
seq_det_sm:
process(clk,rst,en,x,y)
begin
if(rst='1')then
seq_det_ps <= start;
elsif(clk'event and clk ='1')then
seq_det_ps <=seq_det_ns;
end if;
z <='0';
case seq_det_ps is
when start =>
if((x='1')and (en='1'))then
seq_det_ns <=one1;
else
seq_det_ns <=start;
end if;
when one1=>
if((x='1')and (en='1'))then
seq_det_ns <=two1s;
elsif((x='0')and (en='1'))then
seq_det_ns<=start;
else
seq_det_ns <=one1;
end if;
when two1s =>
if((x='0')and (en='1'))then
seq_det_ns<=found_it;
else
seq_det_ns<=two1s;
end if;
when found_it=>
z<=not y;
if((x='0')and (en='1'))then
seq_det_ns<=start;
elsif ((x='1')and (en='1'))then
seq_det_ns<=one1;
else
seq_det_ns<=found_it;
end if;
end case;
end process;
end Behavioral;
Title: Design & implementation of MOORE & MELAY FSM to detect an input
sequence.
Moore
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity seq_det_moore is
Port ( din : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end seq_det_moore;
architecture Behavioral of seq_det_moore is
type state is(st0,st1,st2,st3);
signal present_state,next_state : state;
begin
synchronous_process: process(clk)
begin
if rising_edge(clk)
then
if(rst = '1')then
present_state <= st0;
else
present_state <= next_state;
end if ;
end if;
end process;
output_decoder: process(present_state,din)
begin
next_state <= st0;
case(present_state) is when st0 =>
if(din = '1') then
next_state <= st1;
else
next_state <= st0;end
if; when st1 =>
if(din = '1') then
next_state <= st1;
else
next_state <= st2;end
if; when st2 =>
if(din = '1') then
next_state <= st3;
else
next_state <= st0;end
if; when st3 =>
if(din = '1') then
next_state <= st1;
else
next_state <= st2;end
if;when others =>
next_state <= st0;end
case; end process;
next_state_decoder: process(present_state)
begin case
(present_state) is when st0 =>
dout <= '0';when st1 =>
dout <= '0';when st2 =>
dout <= '0'; when st3 =>
dout <= '1';when others =>
dout <= '0';
end case;
end process;
end Behavioral;
Test Bench :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_seq_det_moore IS
END tb_seq_det_moore;
ARCHITECTURE behavior OF tb_seq_det_moore IS
COMPONENT seq_det_moore
PORT(
din : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;
signal din : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal dout : std_logic;
constant clk_period : time := 10 ns;
BEGIN
uut: seq_det_moore PORT MAP (
din => din,
clk => clk,
rst => rst,
dout => dout
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
wait;
end process;
END;
Melay:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity seq_det_melay is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end seq_det_melay;
architecture Behavioral of seq_det_melay is
type state is(st0,st1,st2,st3);
signal present_state,next_state : state;
begin
synchronous_process:
process(clk)
begin
if rising_edge(clk)
then
if(rst = '1')then
present_state <= st0;
else
present_state <= next_state;
end if ;
end if;
end process;
next_state_and_output_decoder:
process(present_state,din)
begin
dout <= '0';
case(present_state) is when st0 =>
if(din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when st1 =>
if(din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when st2 =>
if(din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =>
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;
TestBench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL
ENTITY tb_seq_det_melay IS
END tb_seq_det_melay;
ARCHITECTURE behavior OF tb_seq_det_melay IS
COMPONENT seq_det_melay
PORT(
clk : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;
signal clk : std_logic := '0';
signal din : std_logic := '0';
signal rst : std_logic := '0';
signal dout : std_logic;
constant clk_period : time := 10 ns;
BEGIN
uut: seq_det_melay PORT MAP (
clk => clk,
din => din,
rst => rst,
dout => dout
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst <= '1';
wait for 100 ns;
rst <= '0';
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
wait;
end process;
END;
Title: Design and implementation of single port RAM with asynchronous read
input.
Single port RAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
Port ( clk,we : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (4 downto 0);
di : in STD_LOGIC_VECTOR (3 downto 0);
do : out STD_LOGIC_VECTOR (3 downto 0));
end RAM;
architecture Behavioral of RAM is
type ram_type is array (31 downto 0)of std_logic_vector(3 downto 0);
signal ram:ram_type;
begin
process(clk)
begin
if(clk'event and clk='1')then
if(we='1')then
ram(conv_integer(a))<=di;
end if;
end if;
end process;
do<=ram(conv_integer(a));ss
end Behavioral;
Title : Design & implementation of 4-bit general purpose ALU using CASE
statement.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_4BIT is
Port ( A : in signed(3 downto 0);
B : in signed(3 downto 0);
SEL : in STD_LOGIC_VECTOR (2 downto 0);
out_alu : out signed(3 downto 0));
end ALU_4BIT;
architecture Behavioral of ALU_4BIT is
begin
process(A ,B,SEL)
begin
case SEL is
when "000" =>
out_alu<= A + B; --addition
when "001" =>
out_alu<= A - B; --subtraction
when "010" =>
out_alu<= A - 1; --sub 1
when "011" =>
out_alu<= A+ 1; --add 1
when "100" =>
out_alu<= A and B; --AND gate
when "101" =>
out_alu<= A or B; --OR gate
when "110" =>
out_alu<= not A; --NOT gate
when "111" =>
out_alu<= A xor B; --XOR gate
when others =>
NULL;
end case;
end process;
end Behavioral;
TESTBENCH code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY TB_ALU_4BIT IS
END TB_ALU_4BIT;
ARCHITECTURE behavior OF TB_ALU_4BIT IS
COMPONENT ALU_4BIT
PORT(
A : IN signed(3 downto 0);
B : IN signed(3 downto 0);
SEL : IN std_logic_vector(2 downto 0);
out_alu : OUT signed(3 downto 0)
);
END COMPONENT;
signal A : signed (3 downto 0) := (others => '0');
signal B : signed(3 downto 0) := (others => '0');
signal SEL : std_logic_vector(2 downto 0) := (others => '0');
signal out_alu : signed(3 downto 0);
BEGIN
uut: ALU_4BIT PORT MAP (
A => A,
B => B,
SEL => SEL,
out_alu => out_alu
);
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "1001";
B <= "1111";
SEL<= "000";
wait for 100 ns;
SEL<= "001";
wait for 100 ns;
SEL<= "010";
wait for 100 ns;
SEL<= "011";
wait for 100 ns;
SEL<= "100";
wait for 100 ns;
SEL<= "101";
wait for 100 ns;
SEL<= "110";
wait for 100 ns;
SEL<= "111";
wait for 100 ns;
end process;
END;
Title: Realization of 4-bit UP counter using VHDL statements.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FOUR_BIT_UPDOWN_COUNTER is
Port ( clk : in STD_LOGIC;
cs : in STD_LOGIC;
op : out STD_LOGIC_VECTOR(3 downto 0));
end FOUR_BIT_UPDOWN_COUNTER;
architecture Behavioral of FOUR_BIT_UPDOWN_COUNTER is
signal temp:std_logic_vector(3 downto 0):=(others=>'0');
begin
process(clk,cs)
begin
if(clk'event and clk='1')then
if(cs='1')then
temp<=temp+1;
else
temp<=temp-1;
end if;
end if;
end process;
op <= temp;
end Behavioral;
Title: Implementation and testing of 0 to 99 Up-Counter with the help of
available peripheral card
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COUNTER_0_to_99 is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
op1 : out STD_LOGIC_VECTOR (6 downto 0);
op2 : out STD_LOGIC_VECTOR (6 downto 0);
sel1 : out STD_LOGIC;
sel2 : out STD_LOGIC);
end COUNTER_0_to_99;
architecture Behavioral of COUNTER_0_to_99 is
signal temp1,temp2: std_logic_vector(3 downto 0):="0000";
begin
process(clk,rst)
begin
if(rst='1') then
temp1<="0000";
temp2<="0000";
elsif(clk='1' and clk' event) then
temp1<=temp1+"0001";
if(temp1="1001") then
temp1<="0000";
temp2<=temp2 + "0001";
end if;
if (temp2="1001")then
temp2<="0000";
end if;
end if;
end process;
op1<="0000001" when temp1 = "0000" else
"1001111" when temp1 = "0001" else
"0010010" when temp1 = "0010" else
"0000110" when temp1 = "0011" else
"1001100" when temp1 = "0100" else
"0100100" when temp1 = "0101" else
"0100000" when temp1 = "0110" else
"0001111" when temp1 = "0111" else
"0000000" when temp1 = "1000" else
"0000100" when temp1 = "1001" else
"1111111";
op2<="0000001" when temp1 = "0000" else
"1001111" when temp1 = "0001" else
"0010010" when temp1 = "0010" else
"0000110" when temp1 = "0011" else
"1001100" when temp1 = "0100" else
"0100100" when temp1 = "0101" else
"0100000" when temp1 = "0110" else
"0001111" when temp1 = "0111" else
"0000000" when temp1 = "1000" else
"0000100" when temp1 = "1001" else
"1111111";
end Behavioral;
Title: Realization of 3:8 decoder using Verilog HDL.
3:8 decoder using verilog :
module decoder3to8_verilog(
input [2:0] sel,
output reg [7:0] out1
);
always@(sel,out1)
case(sel)
3'b000 :out1=8'b00000001;
3'b001 :out1=8'b00000010;
3'b010 :out1=8'b00000100;
3'b011 :out1=8'b00001000;
3'b100 :out1=8'b00010000;
3'b101 :out1=8'b00100000;
3'b110 :out1=8'b01000000;
default :out1=8'b10000000;
endcase
endmodule
Test Bench Code for 3:8 Decoder(verilog) :
module decoder3to8_verilog_tb;
// Inputs
reg [2:0] sel;
// Outputs
wire [7:0] out1;
// Instantiate the Unit Under Test (UUT)
decoder3to8_verilog uut (
.sel(sel),
.out1(out1)
);
initial begin
// Initialize Inputs
sel = 3'b000;
#100;
sel = 3'b001;
#100;
sel = 3'b010;
#100;
sel = 3'b011;
#100;
sel = 3'b100;
#100;
sel = 3'b101;
#100;
sel = 3'b110;
#100;
sel = 3'b111;
#100;
end
endmodule
Title : Design & implementation of 8 bit comparator using Verilog
module bit_8_comparator_verilog(
input [7:0]a,
input [7:0]b,
output a_gt_b,
output a_lt_b,
output a_eq_b
);
assign a_gt_b=(a>b);
assign a_lt_b=(a<b);
assign a_eq_b=(a==b);
endmodule
Test bench of 8 bit comparator using verilog HDL:
module tb_Bit_8_comparator;
// Inputs
reg [7:0] a;
reg [7:0] b;
// Outputs
wire a_gt_b;
wire a_lt_b;
wire a_eq_b;
// Instantiate the Unit Under Test (UUT)
Bit_8_comparator uut (
.a(a),
.b(b),
.a_gt_b(a_gt_b),
.a_lt_b(a_lt_b),
.a_eq_b(a_eq_b));
initial begin
// Initialize Inputs
a=8'b00000000;
b=8'b11111111;
#100;
a=8'b11011010;
b=8'b11011010;
#100;
a=8'b01010101;
b=8'b01010101;
#100;
a=8'b0000000;
b=8'b1111111;
#100;
a=8'b11101011;
b=8'b11101011;
#100;
a=8'b10101111;
b=8'b10101111;
#100;
a=8'b01011101;
b=8'b01011101;
#100;
a=8'b11100101;
b=8'b11100101;
#100;
// Add stimulus her
end
endmodule
Title : Design & implementation of 4-bit up counter using verilog.
module up_counter_verilog_4(
input clk,
input rst,
output [3:0] dout
);
reg[3:0]dout;
wire clk;
wire rst;
initial dout = 0;
always @(posedge(clk))begin
if(rst)
dout <= 0;
else
dout <= dout + 1;
end
endmodule
Title: Implement D-flipflop for no reset, asynchronous rest and synchronous
reset using Verilog HDL.
Asynchronous reset
timescale 1ns / 1ps
module dff_verilog(
input clk,
input reset,
input d,
output reg q
);
always @(posedge clk, negedge reset) begin
if(!reset) begin
q <= 1'b0;
end else begin
q<=d;
end
end
endmodule
Test Bench:
`timescale 1ns / 1ps
module tb_dff_verilog;
reg clk;
reg reset;
reg d;
wire q;
dff_verilog uut (
.clk(clk),
.reset(reset),
.d(d),
.q(q)
);
initial begin
clk = 0;
reset = 0;
d = 0;
#100;
clk = 1;
reset = 0;
d = 0;
#100;
clk = 0;
reset = 1;
d = 0;
#100;
clk = 1;
reset = 1;
d = 0;
#100;
clk = 0;
reset = 0;
d = 1;
#100;
clk = 1;
reset =0;
d = 1;
#100;
clk = 0;
reset = 1;
d = 1;
#100;
clk =1;
reset = 1;
d = 1;
#100;
end
endmodule
Synchronous reset
`timescale 1ns / 1ps
module dff_verilog_syn(
input clk,
input reset,
input d,
output reg q
);
always @(posedge clk) begin
if(reset) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
Test Bench:
`timescale 1ns / 1ps
module tb_dff_verilog_syn;
reg clk;
reg reset;
reg d;
wire q;
dff_verilog_syn uut (
.clk(clk),
.reset(reset),
.d(d),
.q(q)
);
initial begin
clk = 0;
reset = 0;
d = 0;
#100;
clk = 1;
reset = 0;
d = 0;
#100;
clk = 0;
reset = 1;
d = 0;
#100;
clk = 1;
reset = 1;
d = 0;
#100;
clk = 0;
reset = 0;
d = 1;
#100;
clk = 1;
reset =0;
d = 1;
#100;
clk = 0;
reset = 1;
d = 1;
#100;
clk =1;
reset = 1;
d = 1;
#100;
end
endmodule
N0 reset:
`timescale 1ns / 1ps
module dff_verilog_noreset(
input clk,
input d,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule
Test Bench:
`timescale 1ns / 1ps
module tb_dff_verilog_noreset;
reg clk;
reg d;
wire q;
dff_verilog_noreset uut (
.clk(clk),
.d(d),
.q(q)
);
initial begin
clk = 0;
d = 0;
#100;
clk = 0;
d = 1;
#100;
clk = 1;
d = 0;
#100;
clk = 1;
d = 1;
#100;
end
endmodule
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